/*
 * ads119x.h
 *
 *  Created on: 2013. 7. 17.
 *      Author: Shim
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef ADS119X_H_
#define ADS119X_H_

/* Includes ------------------------------------------------------------------*/

/* Exported typdef ------------------------------------------------------------*/
typedef struct _spiCmdData{
	uint8_t cmd;
	uint8_t receivedLength;
	uint8_t null;
}SPI_CMD_DATA;

typedef union {
	SPI_CMD_DATA s;
	uint8_t c[sizeof(SPI_CMD_DATA)];
}SPI_CMD_DATA_U;

typedef struct _spiAdcData {
	uint8_t stat2;
	uint8_t stat1;
	uint8_t stat0;
	uint16_t ch1;
	uint16_t ch2;
	uint16_t ch3;
	uint16_t ch4;
}__attribute__((packed))SPI_ADC_DATA;

typedef union {
	SPI_ADC_DATA s;
	uint8_t c[sizeof(SPI_ADC_DATA)];
}SPI_ADC_DATA_U;
/* Exported constants --------------------------------------------------------*/
/*
 * OP code definition
 */

#define ADC_CMD_WAKEUP			0x02	///< Wake-up from standby mode. NOP command in normal mode
#define ADC_CMD_STANDBY			0x04	///< Enter standby mode
#define ADC_CMD_RESET			0x06	///< Reset the device
#define ADC_CMD_START			0x08	///<  Start/restart conversion
#define ADC_CMD_STOP			0x0A	///< Stop Conversion

#define ADC_CMD_RDATAC			0x10	///< Enable read data continuous mode. this mode is the default mode at power-up
#define ADC_CMD_SDATAC			0x11h	///< Stop read data continuously mode
#define ADC_CMD_RDATA			0x12h	///< Read data by command : supports multiple read back
#define ADC_CMD_RREG			0x20	///< Read n nnnn registers starting at address rrrr
#define ADC_CMD_WREG			0x40	///< write n nnnn regsiters


/*
 * Register Map
 */

// Device setting. (Read-only Registers)
#define ADC_REG_ID_ADDR			0x00

/** Global settings across channels) */
#define ADC_REG_CONFIG1			0x01
#define ADC_REG_CONFIG2			0x02
#define ADC_REG_CONFIG3			0x03
#define ADC_REG_LOFF			0x04

// Channel - Specific setting
#define ADC_REG_CH1SET			0x05
#define ADC_REG_CH2SET			0x06
#define ADC_REG_CH3SET			0x07
#define ADC_REG_CH4SET			0x08
#define ADC_REG_CH5SET			0x09
#define ADC_REG_CH6SET			0x0A
#define ADC_REG_CH7SET			0x0B
#define ADC_REG_CH8SET			0x0C
#define ADC_REG_RLD_SENSP		0x0D
#define ADC_REG_RLD_SENSN		0x0E
#define ADC_REG_LOFF_SENSP		0x0F
#define ADC_REG_LOFF_SENSN		0x10
#define ADC_REG_LOFF_FLIP		0x11

// Lead-off status registers
#define ADC_REG_LOFF_STATP		0x12
#define ADC_REG_LOFF_STATN		0x13

// GPIO and other registers
#define ADC_REG_GPIO			0x14
#define ADC_REG_PACE			0x15
#define ADC_REG_RESERVED		0x16
#define ADC_REG_CONFIG4			0x17
#define ADC_REG_WCT1			0x18
#define ADC_REG_WCT2			0x19

#define BIT0					0x01
#define BIT1					0x02
#define BIT2					0x04
#define BIT3					0x08
#define BIT4					0x10
#define BIT5					0x20
#define BIT6					0x40
#define BIT7					0x80

// Register bits definition
// ID (0x00)
#define ADC_DEV_ID5				BIT7
#define ADC_DEV_ID4				BIT6
#define ADC_DEV_ID3				BIT5
#define ADC_DEV_ID2				BIT2
#define ADC_DEV_ID1				BIT1
#define ADC_DEV_ID0				BIT0

// CONFIG1
#define ADC_N_DAISY_EN			BIT6
#define ADC_N_CLK_EN			BIT5
#define ADC_DR2					BIT2
#define ADC_DR1					BIT1
#define ADC_DR0					BIT0

// CONFIG2
#define ADC_INT_TEST			BIT4
#define ADC_TEST_AMP			BIT2
#define ADC_TEST_FREQ1			BIT1
#define ADC_TEST_FREQ2			BIT0

// CONFIG3
#define ADC_N_PD_REFBUF			BIT7
#define ADC_VREF_4V				BIT5
#define ADC_RLD_MEAS			BIT4
#define ADC_RLDREF_INT			BIT3
#define ADC_N_PD_RLD			BIT2
#define ADC_


// Device ID
#define ADS_119X_ID				0xA0

#define ADS_1194_ID				0x00
#define ADS_1196_ID				0x01
#define ADS_1198_ID				0x02

// Data Rate
#define ADC_SAMPLE_MASK			0xF8
#define ADC_SAMPLE_8K			0x00
#define ADC_SAMPLE_4K			0x01
#define ADC_SAMPLE_2K			0x02
#define ADC_SAMPLE_1K			0x03
#define ADC_SAMPLE_500			0x04		// default value
#define ADC_SAMPLE_250			0x05
#define ADC_SAMPLE_125			0x06

// Channel set
#define ADC_PGA_GAIN_MASK		0x70
#define ADC_PGA_GAIN_6			0x00
#define ADC_PGA_GAIN_1			0x10
#define ADC_PGA_GAIN_2			0x20
#define ADC_PGA_GAIN_3			0x30
#define ADC_PGA_GAIN_4			0x40
#define ADC_PGA_GAIN_8			0x50
#define ADC_PGA_GAIN_12			0x60

#define ADC_CH_INPUT_MASK		0x07
#define ADC_CH_INPUT_NORMAL		0x00
#define ADC_CH_INPUT_SHORTED	0x01
#define ADC_CH_INPUT_RLD_MEAS	0x02
#define ADC_CH_INPUT_MVDD		0x03
#define ADC_CH_INPUT_TEMP		0x04
#define ADC_CH_INPUT_TEST		0x05
#define ADC_CH_INPUT_RLD_DRP	0x06		///< positive electrode is the driver)
#define ADC_CH_INPUT_RLD_DRN	0x07

/* Exported macro ------------------------------------------------------------*/
#define ADC_SET_CONFIG1(daisy_en,clk_en,dr)	(((daisy_en) << 6) | ((clk_en) << 5) | (dr))
#define ADC_SET_CONFIG2(int_test,test_amp,test_freq) (1 << 5 | ((int_test) << 4) | ((test_amp) << 2) | ((test_freq)))
#define ADC_SET_CONFIG3(pd_refbuf,vref_4v,rld_meas,rldref_int,pd_rld,rld_loff_sens,rld_stat)  \
	((((pd_refbuf) & 0x80)<<7)|(((vref_4v) & 0x20)<<5) | (((rld_meas) & 0x10)<<4) | \
	(((rldref_int) & 0x08)<<3)|(((pd_rld) & 0x04)<<2) | (((rld_loff_sens) & 0x02)<<1) | ((rld_stat) & 0x01))
#define ADC_SET_CONFIG4(single_shot, wct_to_rld, pd_loff_comp) (((single_shot)<<3) | ((wct_to_rld) << 2) | ((pd_loff_comp) << 1))

#define ADC_GET_DAISY(config1)				(((config1) & 0x40) >> 6)
#define ADC_GET_clken(config1)				(((config1) & 0x20) >> 5)
#define ADC_GET_DR(config1)					((config1) & 0x07)


#define ADC_GET_INT_TEST(config2)					(((config2) & 0x10 )>> 4)
#define ADC_GET_TEST_AMP(config2)					(((config2) & 0x04) >> 2)
#define ADC_GET_TEST_FREQ(config2)					((config2) & 0x03)

#define ADC_GET_PD_REFBUF(config3)			(((config3) & 0x80) >> 7)
#define ADC_GET_VREF_4V(config3)			(((config3) & 0x20) >> 5)
#define ADC_GET_RLD_MEAS(config3)			(((config3) & 0x10) >> 4)
#define ADC_GET_RLDREF_INT(config3)			(((config3) & 0x08) >> 3)
#define ADC_GET_PD_RLD(config3)				(((config3) & 0x04) >> 2)
#define ADC_GET_RLD_LOFF_SENS(config3)		(((config3) & 0x02) >> 1)
#define ADC_GET_RLD_STAT(config3)			((config3) & 0x01)

#define ADC_GET_SINGLESHOT(config4)			(((config4) & 0x08) >> 3)
#define ADC_GET_WCT_TO_RLD(config4)			(((config4) & 0x04) >> 2)
#define ADC_GET_PD_LOFF_COMP(conffig4)		(((config4) & 0x02) >> 1)

#define ADC_SET_CHANNEL(pd,gain,mux)		(((pd) <<7 ) | ((gain) < 4) | ((mux))
#define ADC_GET_PD(channel)					(((channel) & 0x80) >> 7)
#define ADC_GET_GAIN(channel)				(((channel) & 0x70) >> 4)
#define ADC_GET_MUX(channel)				((channel) & 0x07)

#define ADC_GET_FAMILY_ID(id)				(((id) & 0xe0)>> 5)
#define ADC_GET_CHIP_ID(id)					((id) & 0x07)

/* ID */
#define ADC_FAMILY_ID_RESERVED_1		0x00
#define ADC_FAMILY_ID_RESERVED_2		0x03
#define ADC_FAMILY_ID_RESERVED_3		0x04
#define ADC_FAMILY_ID_ADS119x			0x05
#define ADC_FAMILY_ID_RESERVED_4		0x06
#define ADC_FAMILY_ID_RESERVED_5		0x07

#define ADC_CHIP_ID_1194				0x00
#define ADC_CHIP_ID_1196				0x01
#define ADC_CHIP_ID_1198				0x02
#define ADC_CHIP_RESERVED				0x03

/* Config 1 */
#define ADC_DAISY_MODE					0x00		// default
#define ADC_MULTIPLE_READBACK			0x01
#define ADC_CLOCK_OUTPUT_DISABLED		0x00		// default
#define ADC_CLOCK_OUTPUT_ENABLED		0x01

#define ADC_DR_8KSPS					0x00
#define ADC_DR_4KSPS					0x01
#define ADC_DR_2KSPS					0x02
#define ADC_DR_1KSPS					0x03
#define ADC_DR_500SPS					0x04		// default
#define ADC_DR_250SPS					0x05
#define ADC_DR_125SPS					0x06

/* Config 3 */
#define ADC_PD_INTERNAL_REF_BUF			0x00
#define ADC_EN_INTERNAL_REF_BUF			0x01
#define ADC_VREF_SET_2_4V				0x00
#define ADC_VREF_SET_4V					0x01
#define ADC_RLD_MEASURE_OPEN			0x00		// default
#define ADC_RLD_MEAUSRE_CONNECT			0x01
#define ADC_RLDREF_EXTERNAL				0x00
#define ADC_RLDREF_INTERNAL				0x01
#define ADC_PD_RLD						0x00		// default
#define ADC_EN_RLD						0x01
#define ADC_RLD_LOFF_SENS_DISABLE		0x00		// default
#define ADC_RLD_LOFF_SENS_ENABLE		0x01
#define ADC_RLD_STAT_CONNECTED			0x00		// default
#define ADC_RLD_STAT_DISCONNECTED		0x01

/* Config 4*/
#define ADC_CONT_MODE					0x00		// default
#define ADC_SINGLE_SHOT_MODE			0x01
#define ADC_WCT_TO_RLD_DISCONNECT		0x00		// default
#define ADC_WCT_TO_RLD_CONNECT			0x01

#define ADC_PD_LOFF_COMP_DISABLE		0x00		// default
#define ADC_PD_LOFF_COMP_ENABLE			0x01`
/* Channel */
#define ADC_CH_POWER_NORMAL				0x00 		// default
#define ADC_CH_POWER_DOWN				0x01

#define ADC_CH_GAIN_6					0X00		// default
#define ADC_CH_GAIN_1					0x01
#define ADC_CH_GAIN_2					0x02
#define ADC_CH_GAIN_3					0x03
#define ADC_CH_GAIN_4					0x04
#define ADC_CH_GAIN_8					0x05
#define ADC_CH_GAIN_12					0x06

#define ADC_CH_MUX_NORMAL				0x00		// default
#define ADC_CH_MUX_INPUT_SHORT			0x01
#define ADC_CH_MUX_RLD_MEAS				0x02
#define ADC_CH_MUX_MVDD_MEAS			0x03
#define ADC_CH_MUX_TEMP_SENSOR			0x04
#define ADC_CH_MUX_TEST_SIGNAL			0x05
#define ADC_CH_RLD_DRP					0x06
#define ADC_CH_RLD_DRN					0x07
/* Exported variables ------------------------------------------------------- */

/* Exported functions ------------------------------------------------------- */
#endif /* ADS119X_H_ */
